By S. Takagi (auth.), Dr. Athanasios Dimoulas, Evgeni Gusev, Professor Paul C. McIntyre, Professor Marc Heyns (eds.)
Will nanoelectronic units proceed to scale in line with Moore’s legislation? At this second, there is not any effortless solution on account that gate scaling is quickly rising as a major roadblock for the evolution of CMOS expertise. Channel engineering in line with high-mobility semiconductor fabrics (e.g. strained Si, replacement orientation substrates, Ge or III-V compounds) may possibly aid conquer the hindrances when you consider that they provide functionality enhancement. There are numerous issues notwithstanding. will we understand how to make complicated engineered substrates (e.g. Germanium-on-Insulator)? that are the simplest interface passivation methodologies and (high-k) gate dielectrics on Ge and III-V compounds? do we strategy those fabrics briefly channel transistors utilizing flows, toolsets and understand how just like that during Si know-how? How do those fabrics and units behave on the nanoscale? The reader gets a transparent view of what has been performed thus far, what's the cutting-edge and that are the most demanding situations forward sooner than we come any as regards to a potential Ge and III-V MOS technology.
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Additional resources for Advanced Gate Stacks for High-Mobility Semiconductors
For example, (1) limited performance improvement in p-channel MOSFETs with small or moderate strain (2) wafer quality including defects and dislocations (3) wafer cost (4) increase in junction leakage current. Also, the importance of reducing the parasitic resistance in source/drain regions has been pointed out for higher performance enhancement in ultra-short gate lengths [31, 63]. 2 Local Strain Technology As a technology to solve the above issues associated with global strain techniques, “local strain technology”, which introduces structures and materials to induce strain into channels locally inside MOSFETs, has recently stirred keen interest.
The HF-treated Si(110) surface easily forms a native oxide by air exposure because oxygen can easily reach to the back bond of a hydrogen terminated on Si atom. It is concluded that wet processes and transfer atmosphere before each new process at which the silicon surface must not be oxidized must be carried out in an atmosphere from which oxygen and moisture are removed. By using a alkali- and oxygen-free cleaning method, radical oxidation and moisture free wafer transfer, high performance, low noise and high reliability ULSI can be realized on the Si(110) surface.
A) AFM image and (b) STM image of (110) silicon surface after UPW ﬁnal rinse at RCA cleaning. The lines like trough to the −110 direction are observed are taken to be 2 and 3, respectively  and si is dielectric constant of a silicon. µeﬀ of the p-MOSFET on Si(110) is much larger than that on Si(100) and is also larger than that reported µeﬀ on Si(110) [4,21,22]. This may result from the formation of higher-quality oxides on the Si/SiO2 interface using radical oxidation. However, µeﬀ of the n-MOSFET on Si(110) is the same as that reported previously for Si(110)  and less than that for Si(100).
Advanced Gate Stacks for High-Mobility Semiconductors by S. Takagi (auth.), Dr. Athanasios Dimoulas, Evgeni Gusev, Professor Paul C. McIntyre, Professor Marc Heyns (eds.)